FIG. 7 shows a basic circuit construction of a prior art digital correlator.
In the figure, R and S represent N bit shift registers; Ex-NOR.sub.1 .about.NOR.sub.N exclusive NOR gates; and ADDER an adder. The N bit register R is loaded in serial with N bit reference data REFERENCE in synchronism with a clock RCLOCK. On the other hand, the N bit register S is loaded in serial with information data DATA in synchronism with another clock SCLOCK. It is detected by the Ex-NOR.sub.1 .about.NOR.sub.N gates whether the contents of the registers are in accordance or not in accordance with each other for every bit and the total number of bits, which are in accordance with each other, is obtained by the adder ADDER.
In the case where the digital correlator as indicated in FIG. 7 is used in SSC, it is necessary to set previously reference data by means of external circuits, e.g. a microprocessor 1 and a memory 2, as indicated in FIG. 8.
However, in the case where reference data are changed frequently, or in the case where the reference data are very long, etc., inconveniences such as elongation of the time necessary for changing the reference data, lowering in utilization efficiency of the microprocessor 1 and the memory 2, etc. are produced.